Random access memory (RAM) provides fast, cost-effective, volatile storage for computing devices. The Joint Electron Device Engineering Council (JEDEC) provides memory standards for storage devices. DDR4 SDRAM (double data rate fourth generation synchronous dynamic random-access memory) provides higher module density, lower voltage specifications and higher data rate transfer speeds. DDR4 LRDIMM (load reduced dual in-line memory module) technology uses a distributed buffer approach to implement memory bandwidth efficiencies when scaling to higher capacities and data rate transfer speeds.
With the advancement of DDR memory interfaces, the DDR4 memory currently operates at a data rate up to 3.2 gigabits per second. At such data rates, integrity and timing become more challenging and difficult. As speed goes higher, drivers switch more often, rising/falling edges become sharper and larger switching currents are introduced. Switching currents contribute to power consumption, and introduce power noise that causes jitter, duty cycle degradation through power wire parasitic resistor and package/printed circuit board parasitic inductors.
It would be desirable to implement signal driver slew rate control.